1. Technical Field of the Invention
The present invention relates to the field of integrated circuit, and more particularly to three-dimensional memory (3D-M).
2. Prior Arts
Three-dimensional memory (3D-M) is a monolithic semiconductor memory comprising a plurality of vertically stacked memory levels. It includes three-dimensional read-only memory (3D-ROM) and three-dimensional random-access memory (3D-RAM). The 3D-ROM can be further categorized into three-dimensional mask-programmed read-only memory (3D-MPROM) and three-dimensional electrically-programmable read-only memory (3D-EPROM). Depending on its programming mechanism, 3D-M can comprise a memristor memory, a resistive random-access memory (RRAM or ReRAM), a phase-change memory (PCM), a programmable metallization memory (PMM), or a conductive-bridging random-access memory (CBRAM).
U.S. Pat. No. 5,835,396 issued to Zhang on Nov. 3, 1998 discloses a 3D-M, more particularly a 3D-ROM. As illustrated in FIG. 1A, a 3D-M die 20 comprises a substrate level OK and a plurality of vertically stacked memory levels 16A, 16B. The substrate level OK comprises transistors Ot and interconnects Oi. Transistors Ot are formed in a semiconductor substrate O, while interconnects Oi, including substrate metal layers OM1, OM2, are formed above the substrate O but below the lowest memory level 16A. The memory levels (e.g. 16A) are coupled to the substrate O through contact vias (e.g. 1av).
Each of the memory levels (e.g. 16A) comprises a plurality of upper address lines (e.g. 2a), lower address lines (e.g. 1a) and memory cells (e.g. 5aa). The memory cells could comprise diodes, transistors or other devices. Among all types of memory cells, the diode-based memory cells are of particular importance because they have the smallest size of ˜4F2, where F is the minimum feature size. Since they are generally formed at the cross points between the upper and lower address lines, the diode-based memory cells form a cross-point array. Hereinafter, diode is broadly interpreted as any two-terminal device whose resistance at the read voltage is substantially lower than when the applied voltage has a magnitude smaller than or polarity opposite to that of the read voltage. In one exemplary embodiment, diode is a semiconductor diode, e.g. p-i-n silicon diode. In another exemplary embodiment, diode is a metal-oxide diode, e.g. titanium-oxide diode, nickel-oxide diode.
The memory levels 16A, 16B form at least a 3D-M array 16, while the substrate level OK comprises the peripheral circuits for the 3D-M array 16. A first portion of the peripheral circuits are located underneath the 3D-M array 16 and referred to as under-array peripheral circuit. A second portion of the peripheral circuits are located outside the 3D-M array 16 and referred to as outside-array peripheral circuits 18. Because the space 17 above the outside-array peripheral circuits 18 does not contain any memory cells, this space is actually wasted.
U.S. Pat. No. 7,383,476 issued to Crowley et al. on Jun. 3, 2008 discloses an integrated 3D-M die 20. It can directly use the power supply 23 from a host and exchange address/data 27 with the host. Here, a host is an apparatus that directly uses the 3D-M, and the address/data 27 used by the host are logical address/data.
As illustrated in FIG. 1B, the integrated 3D-M die 20 comprises a 3D-M core region 22 and an intermediate-circuit region 28. The 3D-M core region 22 comprises a plurality of 3D-M arrays (e.g. 22aa, 22ay) and their decoders (e.g. 24, 24G). These decoders include local decoders 24 and global decoders 24G. The local decoder 24 decodes address/data for a single 3D-M array, while the global decoder 24G decodes global address/data 25 to each 3D-M array. Here, the address/data 25 of the 3D-M core region 22 are physical address/data.
The intermediate-circuit region 28 comprises the intermediate circuits between the 3D-M core region 22 and the host. The intermediate circuit 28 performs voltage, address and/or data conversion between the 3D-M core region 22 and the host. For example, it converts power supply 23 to read voltage VR and/or write (programming) voltage VW; it also converts the logic address/data 27 to the physical address/data 25 and vice versa. The intermediate circuit 28 comprises a read/write-voltage generator (VR/VW-generator) 21 and an address/data translator (A/D-translator) 29. The VR/VW-generator 21 includes a band gap reference generator (precision reference generator) 21B, a VR generator 21R and a charge pump 21W (referring to U.S. Pat. No. 6,486,728, “Multi-Stage Charge Pump”, issued to Kleveland on Nov. 26, 2002). The A/D-translator 29 includes an error checking & correction (ECC) circuit 29E, a page register/fault memory 29P and a smart write controller 29W. The ECC circuit 29E detects and corrects data after they are read out from the 3D-M array(s) (referring to U.S. Pat. No. 6,591,394, “Three-Dimensional Memory Array and Method for Storing Data Bits and ECC Bits Therein” issued to Lee et al. on Jul. 8, 2003). The page register/fault memory 29P serves as an intermediate storage device with respect to the host and the 3D-M array(s). It also performs ECC-encoding (referring to U.S. Pat. No. 8,223,525, “Page Register Outside Array and Sense Amplifier Interface”, issued to Balakrishnan et al. on Jul. 17, 2012). The smart write controller 29W monitors write-error. Once a write-error occurs, it activates the self-repair mechanism to reprogram data to a redundant row (referring to U.S. Pat. No. 7,219,271, “Memory Device and Method for Redundancy/Self-Repair”, issued to Kleveland et al. on May 15, 2007). The prior-art integrated 3D-M die 20 performs voltage, address and data conversion internally.
Generally speaking, the intermediate circuits 28 are outside-array peripheral circuits 18. Because they occupy a large area on the 3D-M die 20, the prior-art integrated 3D-M die 20 has low array efficiency. Here, the array efficiency is defined as the ratio between the total memory area (i.e. the chip area used to store user data) and the total chip area. In 3D-M, the total memory area (AM) is the chip area directly underneath user-addressable bits (i.e. not counting bits a user cannot access) and can be expressed as AM=Ac*CL=(4F2)*C3D-M/N, where Ac is the area of a single memory cell, CL is the storage capacity per memory level, F is the address-line pitch, C3D-M is the total storage capacity of the 3D-M and N is the total number of memory levels in the 3D-M. In the following paragraphs, two 3D-M dies are examined for their array efficiencies.
As a first example, a 3-D one-time-programmable memory (3D-OTP) is disclosed in Crowley et al. “512 Mb PROM with 8 Layers of Antifuse/Diode Cells” (referring to 2003 International Solid-State Circuits Conference, FIG. 16.4.5). This 3D-OTP die has a storage capacity of 512 Mb and comprises eight memory levels manufactured at 0.25 um node. The total memory area is 4*(0.25 um)2*512 Mb/8=16 mm2. With a total chip area of 48.3 mm2, the array efficiency of the 3D-OTP die is ˜33%.
As a second example, a 3-D resistive random-access memory (3D-ReRAM) is disclosed in Liu et al. “A 130.7 mm2 2-Layer 32 Gb ReRAM Memory Device in 24 nm Technology” (referring to 2013 International Solid-State Circuits Conference, FIG. 12.1.7). This 3D-ReRAM die has a storage capacity of 32 Gb and comprises two memory levels manufactured at 24 nm node. The total memory area is 4*(24 nm)2*32 Gb/2=36.8 mm2. With a total chip area of 130.7 mm2, the array efficiency of the 3D-ReRAM die is ˜28%.
In the prior-art integrated 3D-M die 20, its 3D-M arrays are integrated with all of its intermediate-circuit components (including VR/VW-generator and A/D-translator). The integrated 3D-M is thought to be advantageous based on the prevailing belief that integration lowers cost. Unfortunately, this belief is no longer true for a 3D-M. Because the 3D-M arrays use a complex back-end process while their intermediate circuits use a relatively simple back-end process, integrating the 3D-M arrays with their intermediate circuits will force the intermediate circuits to use the expensive manufacturing process for the 3D-M arrays. As a result, integration does not lower the overall cost of the 3D-M, but actually increases it. To make things worse, because they can only use the same number of metal layers (e.g. as few as two) as the 3D-M arrays, the intermediate circuits are difficult to design and occupy a large chip area. Finally, because the 3D-M cells generally require high-temperature processing, the intermediate circuits need to use high-temperature interconnect materials, e.g. tungsten (W). This degrades the 3D-M performance.